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快速銅－銅接點與它們的可靠度議題

為了解決DRAM pitch的問題，作者謝凱程 這樣論述：

由於銅對銅直接接合技術應用於封裝技術逐漸成為三維積體電路封裝的關鍵技術，本論文利用銅(111)平面的快速表面擴散，完成快速銅－銅接合來達到低熱預算接合。在接合溫度300 ℃、壓力15~90 MPa下，接合時間可以縮短到10 秒以內，且接點電阻值為4.5 mΩ。接著利用表面潛變的接合機制推導出一個接合模型，該模型可以藉由接合溫度、壓力、擴散係數、表面粗糙度來預測接合時間，接合界面的有效擴散係數同時也被引入討論接合機制。為了進一步驗證快速銅－銅接合的可靠度，溫度循環測試與電遷移測試被採用來研究銅－銅接點結構的弱點，失效的標準定義為20%電阻上升。在溫度循環測試中，所有接點都通過了1000次循環測

試，在接合界面的中心位置因為在高溫下受到拉應力，所以產生了裂縫，裂縫的範圍跟接合強度高度相關。在電遷移測試方面，如果接合強度不足，在銅－銅接合面會直接斷路，這是第一種的破壞模式。第二種破壞模式是孔洞在銅－銅接點與導線間的接觸面上形成，且聚集成一個扁平大孔洞，該孔洞可能進而造成銅－銅接點與導線間的斷路。最後一種模式是孔洞分散在晶界與銅／接著層界面，這種破壞模式可以達到5000小時以上的壽命。

應用於異質整合平台與下世代微機電系統之先進封裝關鍵技術開發

為了解決DRAM pitch的問題，作者蔡逸杰 這樣論述：

Table of Contents摘 要 iAbstract iv誌 謝 viiiTable Captions xiiiFigure Captions xivChapter 1 Introduction 11.1 General Background 11.2 Heterogeneous integration platform and MEMS encapsulation 31.3 Organization of the thesis 5Chapter 2 Low Thermal Budget Chi

p-level Stacking by Metal Bonding 92.1 Introduction 92.2 Electroless nickel immersion gold (ENIG) to Sn-Cu microbump bonding 112.2.1 Specification of bonding structure and process flow 112.2.2 Bonding mechanism of ENIG-Sn/Cu joint 122.2.3 Bonding joint analyses 132.2

.4 Electrical measurement and reliability test 132.3 Cu pillar to In-Sn-Cu pad bonding with Ni buffer layer 142.3.1 Specification of bonding structure and process flow 142.3.2 Mechanism of Cu pillar to In-Sn-Cu pad bonding with Ni buffer layer …………………………………………………………………………….15

2.3.3 Bonding joint analyses 162.3.4 Electrical measurement and reliability test 172.4 Cu pillar to Cu pillar direct bonding with Pd passivation layer 172.4.1 Specification of bonding structure and process flow 172.4.2 Mechanism of Cu pillar to Cu pillar direct bonding wit

h Pd passivation layer 192.4.3 Bonding joint analyses 202.4.4 Electrical measurement and reliability test 212.5 Demonstration of 2.5D heterogeneous integration with chip-level bumping process 222.5.1 2.5D integration platform scheme 222.5.2 Electrical Property and Relia

bility Test of the 2.5D Platform 232.6 Summary 24Chapter 3 Wafer-on-wafer (WOW) Bumpless TSV Structure for DRAM Application 423.1 Introduction 423.2 Specifications and process flow 443.3 Electrical measurement and reliability test 453.4 New lumped circuit model an

d high frequency simulation 493.5 Summary 52Chapter 4 Highly Productive and Reliable Wafer-level MEMS Packaging …………………………………………………………………….684.1 Introduction 684.2 Au-Sn eutectic bonding v.s. Au-Au direct bonding 704.3 Ultra-thin glass-based wafer-level stacking through

metal bonding 714.4 Stability investigation of metal combination 724.5 Summary 75Chapter 5 Conclusion and Future Work 925.1 Conclusion 925.2 Future Work 94Reference …………………………………………………………………….96簡歷(Vita) …………………………………………………………………...105